Enhancing Portability in High Performance Computing: Designing Fast Scientific Code with Longevity

Portability, an oftentimes sought-after goal in scientific applications, confers a number of possible advantages onto computer code. Portable code will often have greater longevity, enjoy a broader ecosystem, appeal to a wider variety of application developers, and by definition will run on more systems than its pigeonholed counterpart. These advantages come at a cost, however, and a rational approach to balancing costs and benefits requires a systemic evaluation. While the benefits for each application are likely situation-dependent, the costs in terms of resources, including but not limited to time, money, computational power, and memory requirements, are quantifiable. This document will identify strategies for enhancing performance portability on a variety of platforms available to the scientific computing community which will have little or no adverse impact on alternate architectures; this is done by implementing an iterative point solver requiring a high degree of data transfer bandwidth of a type commonly used in high performance applications used for computing a solution to partial differential equations (PDEs). In this thesis, we were able to show significant speed enhancements for architectures as diverse as complex traditional Central Processing Units (CPUs), Graphical Processing Units (GPUs), and Field Programmable Gate Arrays (FPGAs). Employing generalized optimizations on a variety of development frameworks we were able to show as much as a 92.5% reduction on a pipelined architecture (FPGA) while having a negligible impact on alternate architectures, and an 88.6% reduction in execution time on a Single Instruction Multiple Data (SIMD) architecture (GPU/CPU) while also having a negligible impact on alternate architectures. By enforcing these design rules in released versions of scientific code, the code has the potential to be optimally positioned for future advancements in computing architecture as well as being performance portable among existing architectures

Is Ethereum\u27s ProgPoW ASIC Resistant?

Cryptocurrencies are more than a decade old and several issues have been discovered since their then. One of these issues is a partial negation of the intent to “democratize” money by decentralizing control of the infrastructure that creates, transmits, and stores monetary data. The Programmatic Proof of Work (ProgPoW) algorithm is intended as a possible solution to this problem for the Ethereum cryptocurrency. This paper examines ProgPow’s claim to be Application Specific Integrated Circuit (ASIC) resistant. This is achieved by isolating the proof-of-work code from the Ethereum blockchain, inserting the ProgPoW algorithm, and measuring the performance of the new implementation as a multithread CPU program, as well as a GPU implementation. The most remarkable difference between the ProgPoW algorithm and the currently implemented Ethereum Proof-of Work is the addition of a random sequence of math operations in the main loop that require increased memory bandwidth. Analyzing and comparing the performance of the CPU and GPU implementations should provide an insight into how the ProgPoW algorithm might perform on an ASIC